NEC, Elpida and Oki Team develops Terabit 3D Memory Packaging System

NEC Electronics, Elpida Memory and Oki Electric team has developed a 3D layered memory packaging technology. The technology will incorporate eight memory chips and one controller chip in a vertical stack. Each of the chips that are involved in the technology has more than 1000 pins on each side and they are connected to polysilicon electrodes that have been built into the chips that vertically pierce the chips from top to bottom. High density microbumps are then used to interconnect the chips. The key feature of the technology is that the entire stack is quite compact because the chips are only 50 micrometers thick. These compact chips can be used in applications like 3D gaming that require fast memory chips and low power consumption. Other approaches like SoC (System on Chip) and SiP (System in package) that are currently employed for the above applications have their own disadvantages. If you talk about SoC then we have to consider the fact that there is less of available area on a chip that can be used for memory integration, so we cannot integrate large memory on the chip. On the other hand SiP creates impedance balancing problems and that limits the number of pins that can be directly connected to the processor. If we consider the above problems then we have to appreciate the work done by NEC/Elpida/Oki who have managed to develop a solution for the next generation of mobile devices.

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